Inter-Stage Matching Network to Enhance Common Mode Stability

ABSTRACT

An amplifier has a first transistor, a second transistor, a third transistor and a fourth transistor, a first transformation network having first and second grounds and a second transformation network having third and fourth grounds. The amplifier has a collector of the first transistor operatively connected to a base of the third transistor by the first transformation network, a collector of the second transistor operatively connected to a base of the fourth transistor by the second transformation network, the first ground and the third ground are electrically connected to each other, the second ground and the fourth ground are electrically connected to each other, the emitters of the first and of the second transistors are electrically connected to the first ground and the third ground, and the second ground and the fourth ground are electrically connected to the emitters of the third and of the fourth transistors.

CLAIM OF PRIORITY

This application claims priority to U.S. Provisional Application No.60/853,130, filed on Oct. 20, 2006, the entire disclosure of which isincorporated by reference herein.

FIELD OF THE INVENTION

The present invention relates to differential RF/microwave multi-stageintegrated circuit amplifiers, and more particularly to inter-stagematching networks to enhance common mode stability in differentialamplifier designs.

BACKGROUND OF THE INVENTION

Referring to FIG. 1, integrated Circuit RF/Microwave amplifiers aretypically constructed of multiple amplification stages 10, 11 and 12connected in series on a single semiconductor die 05. First stage 10connects to a signal source though an input impedance transformationnetwork (not shown) that may be fabricated on-chip or off-chip, and laststage 12 connects to a load impedance through an output impedancetransformation network (not shown) that also may be fabricated on-chipor off-chip. For amplifiers that have three or more stages, there willbe one or more amplifier stages (for example stage 11) that areterminated on both their input and output by another amplifier stage.This applies to any amplification stage located between first 10 andlast stage 12. The networks connecting these middle stages are referredto as inter-stage transformation networks.

The design and performance of inter-stage transformation networks is amajor contributor to overall amplifier performance. Of particularinterest for this invention is the role that the inter-stage networksplay in preventing unwanted oscillations from occurring in theamplifier. The complexity of the design of inner-stage networks isreduced in many semiconductor technologies due to the presence ofthrough-substrate vias. A through-substrate via is a path thatpenetrates the top semiconductor substrate surface where the active (andpassive) devices are fabricated and connects directly to the bottomsemiconductor substrate surface which is a metalized ground plane. Theprevalent technology in the field of RF/Microwave amplifiers withthrough-substrate vias is Gallium Arsenide (GaAs). For technologies suchas Si and SiGe, through-substrate vias are not an option since there isno bottom ground plane.

When developing RF/Microwave amplifiers in technologies that lackthrough-substrate vias, grounding becomes an important and difficultproblem. The only means for connecting a Si amplifier circuit to groundis through the use of wirebonds that go between the chip and the packageground plane. The parasitic inductance from these wirebonds introduces asignificant amount of inductance between the amplifier circuit andground.

A common method for overcoming grounding problems is to utilize adifferential amplifier topology. As one skilled in the art willunderstand, a differential amplifier topology allows for a virtualground to be generated on-chip that will be independent of the amount ofwirebond inductance present. By making use of this virtual ground, ahigh-performance differential circuit may be designed. Any input signalto a differential amplifier may be separated into differential-mode andcommon-mode components. As the name implies, the differential-modesignal is the primary mode of operation for the amplifier. However thecommon-mode performance of the amplifier must also be considered toensure proper amplifier operation.

The virtual ground created in a differential amplifier is only presentfor differential-mode signals. All of the parasitic wirebond inductanceis present for common-mode signals and presents numerous problems. Ofparticular concern is the reduced stability of the amplifier in thecommon-mode. The primary cause of the reduced common-mode stabilityresults from the inductance caused by wirebonds 13, 14, and 15. Thelarge inductance associated with wirebond 14, which is in series withthe emitters of transistors 43 and 44 can cause devices 43 and 44 tobecome unstable. This is not a concern for the differential-mode signalsince RF current does not flow through the wirebonds as shown by theequivalent differential-mode circuit shown in FIG. 3.

Another approach to reduce the effects of the inductance associated withwirebond 14 is to reduce the common-mode gain in order to improve theactive device's stability. This can be done by adding resistive loss tothe inter-stage network that only affects the common-mode signal. Thisallows for the differential mode signal to be unaffected while helpingto stabilize the common-mode.

SUMMARY OF THE INVENTION

The present invention recognizes and addresses the foregoingconsiderations, and others, of prior art constructions and methods.

These and/or other objects are achieved by an amplifier comprising afirst stage having at least one first transistor, and at least onesecond transistor, a second stage having at least one third transistor,and at least one fourth transistor, a first transformation networkhaving a first ground and a second ground, and a second transformationnetwork having a third ground and a fourth ground. The amplifier has acollector of the at least one first transistor is operatively connectedto a base of the at least one third transistor by the firsttransformation network, a collector of the at least one secondtransistor is operatively connected to a base of the at least one fourthtransistor by the second transformation network, the first ground andthe third ground are electrically connected to each other, the secondground and the fourth ground are electrically connected to each other,an emitter of the at least one first transistor and an emitter of the atleast one second transistor are electrically connected to the firstground and the third ground, and the second ground and the fourth groundare electrically connected to an emitter of the at least one thirdtransistor and an emitter of the at least one fourth transistor.

In one embodiment, the electrical connection between the second and thefourth grounds and the at least one third and the at least one fourthtransistor emitters further comprises a resistor. In another embodiment,the electrical connection between the first and the third grounds andthe electrical connection between the second and fourth grounds areconnected by at least a resistor. In another embodiment, the electricalconnection between the first and the third grounds and the at least onefirst and the at least one second transistor emitters further comprisesa resistor. In yet another embodiment, the electrical connection betweenthe first and the third grounds and the electrical connection betweenthe second and fourth grounds are connected by at least one resistor. Instill other embodiments, the at least one first transistor furthercomprises a plurality of transistors connected in parallel, the at leastone second transistor further comprises a plurality of transistorsconnected in parallel, the at least one third transistor furthercomprises a plurality of transistors connected in parallel, and the atleast one fourth transistor further comprises a plurality of transistorsconnected in parallel.

In some of the embodiments, the electrical connections containparasitics, where the parasitics may contain one or more resistive orinductive properties. In some of these embodiments, the at least onefirst, the at least one second, the at least one third, and the at leastone fourth transistors are bipolar junction transistors. In some ofthese embodiments, the at least one first, the at least one second, theat least one third, and the at least one fourth transistors are bipolarjunction transistors. In yet other of these embodiments, the at leastone first, the at least one second, the at least one third, and the atleast one fourth transistors are field effect transistors. Still inother embodiments, the at least one first, the at least one second, theat least one third, and the at least one fourth transistors are threeterminal transconductance amplifier devices.

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate one or more embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

A full and enabling disclosure of the present invention, including thebest mode thereof directed to one of ordinary skill in the art, is setforth in the specification, which makes reference to the appendedfigures, in which:

FIG. 1 is a simplified schematic diagram of a prior art differentialthree-stage amplifier;

FIG. 2 is a schematic diagram showing two cascaded amplifier stages fromthe diagram of FIG. 1 incorporating an embodiment of this invention;

FIG. 3 is an equivalent circuit of FIG. 2 for the differential-modesignal in accordance with an embodiment of the present invention; and

FIG. 4 is an equivalent circuit of FIG. 2 for the common-mode signal inaccordance with an embodiment of the present invention.

Repeat use of reference characters in the present specification anddrawings is intended to represent same or analogous features or elementsof the invention.

DETAILED DESCRIPTION OF INVENTION

Reference will now be made in detail to presently preferred embodimentsof the invention, one or more examples of which are illustrated in theaccompanying drawings. Each example is provided by way of explanation ofthe invention, not limitation of the invention. In fact, it will beapparent to those skilled in the art that modifications and variationscan be made in the present invention without departing from the scopeand spirit thereof. For instance, features illustrated or described aspart of one embodiment may be used on another embodiment to yield astill further embodiment. Thus, it is intended that the presentinvention covers such modifications and variations as come within thescope of the appended claims and their equivalents.

This invention provides a means for improving common-mode stability inmulti-stage differential amplifiers. Common-mode stability is achievedby implementing circuitry to both reduce common-mode gain, provide anon-chip ground path, and to provide stabilizing positive resistance atthe active device only for the common-mode. Additionally, effectscausing the reduction of amplifier output are minimized by reducing theleakage of signal from one stage of the amplifier to a preceding stage.

Referring to FIG. 2, an on-chip connection 35 is made from the emittersof transistors 41 and 42 to the emitters of transistors 43 and 44. Inaddition to connecting the emitters of the transistors, connection 35also connects to all of the shunt components in inter-stage network 36.The addition of on chip-connection 35 provides an on-chip ground returnpath for the common-mode RF signal between amplifier stages 11 and 12.On-chip connection 35 can be modeled as a series inductance betweenamplifier stages 11 and 12, which is effectively in parallel with theinductances created by wirebonds 13 and 14. The parallel combination ofthe inductances results in an inductance that is smaller than theinductance of wirebonds 13 and 14 individually. However, the resultantparallel inductance is still large enough to cause common-mode stabilityproblems.

To account for the common-mode stability problems caused by theresultant parallel inductance, a resistor, 31, is placed between theemitters of transistors 43 and 44 and the nearest shunt inter-stagenetwork connection 52. Resistor 31 is a series component in the on-chipground connection 35. The addition of resistor 31 has no impact on thedifferential-mode signal, as can be seen in FIG. 3 since in thedifferential mode on-chip connection 35 effectively is seen as ground.Resistor 31, however, does play an important role for common-modesignals, as seen in FIG. 4. In particular, resistor 31 causes theimpedance of the shunt elements connected to node 52 to have a largepositive real component of impedance. This positive real impedancecomponent helps stabilize the input of transistors 43 and 44 bycancelling any potential negative real part impedance generated bytransistors 43 and 44, in addition to increasing the loss of network 36(FIG. 2) for common-mode signals thus reducing the common mode gain ofamplifier 13.

An appropriate value for resistor 31 may be determined through theobservation of the small-signal stability of amplifier stage 11 as thevalue of resistor 31 is varied. Resistor 31 should be of a large enoughvalue to ensure that the amplifier is satisfactorily stable. Rollett'sstability factor (K) may also be used as an appropriate measure ofamplifier stability. As one skilled in the art would recognize, byselecting a value of resistor 31 that results in a Rollett's stabilityfactor of above one at all frequencies of interest, the amplifier shouldbe unconditionally stable. A practical method for determining anappropriate value of resistor 31 is by creating an electrical model ofthe full differential amplifier in FIG. 1, including all wirebondparacitics. One skilled in the art may then use a RF circuit simulator,such as Agilent's Advanced Design System, to simulate this electricalmodel and observe the stability at the input of amplifier stage 11 whendriven with both differential and common mode signals.

Referring to FIG. 4, the addition of on-chip ground connection 35creates a feedback path 35 for signals from amplifier stage 22 back intostage 21. Current exiting the emitters of transistors 43 duringlarge-signal excitation has two ground return paths. One path isdirectly through wirebond 14 and the other path is through on-chipground connection 35 and through wirebond 13 to ground. This pathcreates a feedback signal at the emitters of transistors 41 that mayreduce the amount of output power that amplifier stage 21 is capable ofdelivering. To prevent the reduction of output power from stage 21, anadditional resistor 32 may be placed in on-chip ground connection 35 toisolate the current due to stage 22 by forcing it through wirebond 14rather than both wirebond 13 and 14. This is of particular concern forlarge signal levels as both differential-mode and common-mode signalswill generate currents that can leak from stage 22 back troughconnection 35 into stage 21.

A suitable value for resistor 32 may be determined by observing theeffect of resistor 32 on the differential output power at whichamplifier stage 21 compresses. Resistor 32 should be increased until thecompression level of amplifier stage 21 becomes insensitive to smallvariations in resistor 32. One skilled in the art could perform such ananalysis by performing a harmonic balance simulation, utilizing asimulation tool such as Agilent's Advanced Design System, on a completeelectrical model of the amplifier in FIG. 1. Such a model should includeall wirebond paracitics and incorporate non-linear device models for theactive components.

While one or more preferred embodiments of the invention have beendescribed above, it should be understood that any and all equivalentrealizations of the present invention are included within the scope andspirit thereof. The embodiments depicted are presented by way of exampleonly and are not intended as limitations upon the present invention.Thus, it should be understood by those of ordinary skill in this artthat the present invention is not limited to these embodiments sincemodifications can be made. Therefore, it is contemplated that any andall such embodiments are included in the present invention as may fallwithin the scope and spirit thereof.

1. An amplifier comprising: a. a first stage having i. at least onefirst transistor, and ii. at least one second transistor, wherein anemitter of said at least one first transistor and an emitter of said atleast one second transistor are operatively connected; b. a second stagehaving i. at least one third transistor, and ii. at least one fourthtransistor; wherein an emitter of said at least one third transistor andan emitter of said at least one fourth transistor are operativelyconnected; c. a first transformation network having a first ground and asecond ground; and d. a second transformation network having a thirdground and a fourth ground, wherein a collector of said at least onefirst transistor is operatively connected to a base of said at least onethird transistor by said first transformation network, a collector ofsaid at least one second transistor is operatively connected to a baseof said at least one fourth transistor by said second transformationnetwork, said first ground and said third ground are operativelyconnected to an emitter of said at least one first transistor and anemitter of said at least one second transistor, said second ground andsaid fourth ground are operatively connected to an emitter of said atleast one third transistor and said at least one fourth transistor, andsaid first ground and said second ground are operatively connected by atleast one resistor.
 2. The amplifier of claim 1, wherein a base of saidat least one first transistor and a base of said at least one secondtransistor are operatively coupled to an input of said amplifier.
 3. Theamplifier of claim 2, wherein a collector of said at least one thirdtransistor and a collector of said at least one fourth transistor areoperatively coupled to an output of said amplifier.
 4. The amplifier ofclaim 1, wherein a. said at least one first transistor further comprisesa plurality of transistors connected in parallel; b. said at least onesecond transistor further comprises a plurality of transistors connectedin parallel; c. said at least one third transistor further comprises aplurality of transistors connected in parallel; and d. said at least onefourth transistor further comprises a plurality of transistors connectedin parallel.
 5. An amplifier comprising: a. a first stage having i. afirst transistor, and ii. a second transistor; b. a second stage havingi. a third transistor, and ii. a fourth transistor; c. a firsttransformation network having a first ground and a second ground; and d.a second transformation network having a third ground and a fourthground, wherein a collector of said first transistor is operativelyconnected to a base of said third transistor by said firsttransformation network, a collector of said second transistor isoperatively connected to a base of said fourth transistor by said secondtransformation network, said first ground and said third ground areoperatively connected to each other, said second ground and said fourthground are operatively connected to each other, an emitter of said firsttransistor and an emitter of said second transistor are operativelyconnected to said first ground and said third ground, said first ground,said second ground, said third ground and said fourth ground areelectrically connected to one another, and said second ground and saidfourth ground are electrically connected to an emitter of said thirdtransistor and an emitter of said fourth transistor by at least oneresistor.
 6. The amplifier of claim 5, wherein said electricalconnection contains parasitics.
 7. The amplifier of claim 6, whereinsaid parasitics further comprises resistive properties.
 8. The amplifierof claim 6, wherein said parasitics further comprises inductiveproperties.
 9. An amplifier comprising: a. a first stage having i. afirst plurality of transistors connected in parallel with one another,and ii. a second plurality of transistors connected in parallel with oneanother, wherein each emitter of said first plurality of transistors areoperatively connected to each emitter of said second plurality oftransistors; b. a second stage having i. a third plurality oftransistors connected in parallel with one another, and ii. a fourthplurality of transistor connected in parallel with one another; whereineach emitter of said third plurality of transistors are operativelyconnected to each emitter of said fourth plurality of transistors; c. afirst transformation network having a first ground and a second ground;and d. a second transformation network having a third ground and afourth ground, wherein each collector of said first plurality oftransistors are operatively connected to each base of said thirdplurality of transistors by said first transformation network, eachcollector of said second plurality of transistors are operativelyconnected to each base of said fourth plurality of transistors by saidsecond transformation network, said first ground and said third groundare operatively connected to each emitter of said first plurality oftransistors and each emitter of said second plurality of transistors,said second ground and said fourth ground are operatively connected toeach emitter of said third plurality of transistors and each emitter ofsaid fourth plurality of transistors, and said first, said second, saidthird and said fourth grounds each being electrically connected to oneanother.
 10. The amplifier of claim 9, wherein said electricalconnection further comprises a resistor between said first and saidsecond grounds.
 11. The amplifier of claim 9, wherein said electricalconnection contains parasitics.
 12. The amplifier of claim 11, whereinsaid parasitics further comprises resistive properties.
 13. Theamplifier of claim 12, wherein said parasitics further comprisesinductive properties.
 14. An amplifier comprising: a. a first stagehaving i. at least one first transistor, and ii. at least one secondtransistor; b. a second stage having i. at least one third transistor,and ii. at least one fourth transistor; c. a first transformationnetwork having a first ground and a second ground; and d. a secondtransformation network having a third ground and a fourth ground,wherein a collector of said at least one first transistor is operativelyconnected to a base of said at least one third transistor by said firsttransformation network, a collector of said at least one secondtransistor is operatively connected to a base of said at least onefourth transistor by said second transformation network, said firstground, said third ground, an emitter of said at least one firsttransistor and an emitter of said at least one second transistor areelectrically connected to each other, said second ground, said fourthground, an emitter of said at least one third transistor and an emitterof said at least one fourth transistor are electrically connected toeach other, and said first and said third grounds are electricallyconnected to said second and said fourth grounds.
 15. The amplifier ofclaim 14, wherein said electrical connection between said second andsaid fourth grounds and said at least one third and said at least onefourth transistor emitters comprises at least one resistor.
 16. Theamplifier of claim 15, wherein said first and said third grounds andsaid second and said fourth grounds are connected by at least oneresistor.
 17. The amplifier of claim 14, wherein said electricalconnections contain parasitics.
 18. The amplifier of claim 17, whereinsaid parasitics have resistive properties.
 19. The amplifier of claim18, wherein said parasitics have inductive properties.
 20. The amplifierof claim 14, wherein said first and said third grounds and said secondand said fourth grounds are connected by at least one resistor.
 21. Theamplifier of claim 14, wherein said electrical connection between saidfirst and said third grounds and said at least one first and said atleast one second transistor emitters comprises at least one resistor.22. The amplifier of claim 14, wherein said at least one first, said atleast one second, said at least one third, and said at least one fourthtransistors are bipolar junction transistors.
 23. The amplifier of claim14, wherein said at least one first, said at least one second, said atleast one third, and said at least one fourth transistors are fieldeffect transistors.
 24. The amplifier of claim 14, wherein said at leastone first, said at least one second, said at least one third, and saidat least one fourth transistors are three terminal transconductanceamplifier devices.
 25. The amplifier of claim 14, wherein a. said atleast one first transistor further comprises a plurality of transistorsconnected in parallel; b. said at least one second transistor furthercomprises a plurality of transistors connected in parallel; c. said atleast one third transistor further comprises a plurality of transistorsconnected in parallel; and d. said at least one fourth transistorfurther comprises a plurality of transistors connected in parallel.